{"id":715,"date":"2016-11-29T16:16:20","date_gmt":"2016-11-30T01:16:20","guid":{"rendered":"\/blog\/?p=715"},"modified":"2023-09-21T09:37:52","modified_gmt":"2023-09-21T00:37:52","slug":"arm-%ec%96%b4%ec%85%88%eb%b8%94%eb%a6%ac%ec%96%b4-%ec%a0%95%eb%a6%ac","status":"publish","type":"post","link":"https:\/\/hasu0707.duckdns.org\/blog\/?p=715","title":{"rendered":"ARM \uc5b4\uc148\ube14\ub9ac\uc5b4 \uc815\ub9ac"},"content":{"rendered":"\n
\ucd9c\ucc981 : http:\/\/downrg.com\/417<\/span>
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\ucd9c\ucc982 : http:\/\/achiven.tistory.com\/entry\/%EC%A3%BC%EC%9A%94-ARM-%EC%96%B4%EC%85%88%EB%B8%94%EB%A6%AC-%EB%AA%85%EB%A0%B9<\/span><\/div>
\ucd9c\ucc983 : http:\/\/egloos.zum.com\/recipes\/v\/4986854<\/span><\/div><\/font><\/div>

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>> ARM Reference : <\/span>ARM_Reference-rE.Ejected.pdf<\/span><\/a>\r\n<\/span><\/font><\/div>

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\u25a0 ARM Register\uc640 Context<\/span><\/strong><\/span>
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ARM Core\ub97c \uc798 \uc774\ud574\ud558\uae30 \uc704\ud574\uc11c\ub294 ARM Core\uc5d0 \ub0b4\uc7a5\ub418\uc5b4 \uc788\ub294 \uae30\ubcf8 Register\ub4e4\uc774 \uc5b4\ub5bb\uac8c \uad6c\uc131\ub418\uc5b4 \uc788\uace0, \uc0ac\uc6a9\ub418\ub294\uc9c0\ub97c \uc798 \uc54c\uba74 \uc0c1\ub2f9\ud788 \ud3b8\ub9ac \ud558\uac70\ub4e0\uc694. Register\ub4e4\uc740 Core\uac00 \uc0ac\uc6a9\ud560 \uc218 \uc788\ub294 \uc800\uc7a5 \ub9e4\uccb4 \uc911\uc5d0\uc11c \uac00\uc7a5 \ube60\ub978 \uc18d\ub3c4\ub97c \uc790\ub791\ud558\uba70, ARM\uc758 \ub3d9\uc791\uc740 \ubaa8\ub450 \uc544\ub798\uc758 Register\ub4e4\uc744 \uc5b4\ub5bb\uac8c \uc7a5\ub09c \uce60 \uac83\uc774\ub0d0\uac00 \uadf8 \uc2e4\uccb4\uc774\uc790 \uc815\uccb4 \uc778 \uac70\uc8e0.<\/span><\/div>

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ARM core\ub294 \uc544\ub798\uc758 Register file\uc744 \uac00\uc9c0\uace0 \uc788\uace0\uc694. \uc0c1\ub2f9\ud788 \ubcf5\uc7a1\ud574 \ubcf4\uc774\uc9c0\ub9cc, \ubcc4\uac70 \uc544\ub2d9\ub2c8\ub2e4. ARM core\ub294\ub3d9\uc791 mode\uac00 \ubc14\ub00c\uba74 \uc0ac\uc6a9\ud558\ub294 Register set\ub3c4 \ubc14\ub01d\ub2c8\ub2e4. \uadf8\ub9bc\uacfc \uac19\uc774 7\uac1c\uc758 \ub3d9\uc791 mode\uc5d0 \ub300\ud558\uc5ec \ub808\uc9c0\uc2a4\ud130 set\uc774 \ub530\ub85c \uc874\uc7ac\ud558\uac8c \ub418\uba70, ARM core\ub294 32 bit register\ub97c \ud55c mode\ub2f9 R0~R15\uae4c\uc9c0 16\uac1c\ud558\uace0, CPSR + SPSR\uae4c\uc9c0 \ub354\ud574\uc11c 18\uac1c\uc529 \uac00\uc9c0\uba70, \ucd1d 7\uac1c mode\uac00 \uc788\uc73c\ub2c8\uae4c, 18 registers X 7\uac1c mode = 126\uac1c\uc758 Register\ub97c \uac00\uc9d1\ub2c8\ub2e4....\uc544\uc544\uc544\uc544\uc544\uc544... \uc77c\uc904 \uc54c\uc558\uaca0\uc2b5\ub2c8\ub2e4\ub9cc, \uadf8\ub7ec\uba74 \uc5bc\ub9c8\ub098 \uc88b\uc73c\ub828\ub9cc \uc544~ \ud2c0\ub838\uc2b5\ub2c8\ub2e4.<\/span><\/div>

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ARM core\ub294 \ucd1d 37\uac1c\uc758 register\ub97c \uac00\uc9c0\uace0\uc694. \uc65c\ub0d0! \uc0bc\uac01\ud615\uc774 \uadf8\ub824\uc9c4 register\ub4e4\uc744 banked register\ub77c\uace0 \ubd80\ub974\uba70 \uadf8\uac83\ub4e4\ub9cc\uc774 \uac01 mode\ubcc4\ub85c \ub530\ub85c \uc788\uace0\uc694 \ub098\uba38\uc9c0\ub294 mode\ub9c8\ub2e4 \ubaa8\ub450 \uacf5\uc6a9\uc73c\ub85c \uc0ac\uc6a9\ud569\ub2c8\ub2e4.<\/span><\/div>
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\uadf8\ub7ec\ub2c8\uae4c, \ucd1d<\/span>
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R0~R15 (16\uac1c) + CPSR (1\uac1c) + FIQ\uc758 R8~R14, SPSR (8\uac1c) + SVC\uc758 R13, R14, SPSR (3\uac1c)<\/span><\/div>
+ Abort\uc758 R13, R14, SPSR  (3\uac1c) + IRQ\uc758 R13, R14, SPSR (3\uac1c), UND\uc758 R13, R14, SPSR (3\uac1c)<\/span><\/div>
 = 16 + 1 + 8 + 3 + 3 + 3 + 3= 37\uac1c \uc785\ub2c8\ub2e4.<\/span><\/div>

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\uc774\uac78 \uc2e4\uc81c \ubb3c\ub9ac\uc801\uc73c\ub85c \ubcf4\uba74 \uc774\ub807\uaca0\uc8e0.. \uc73c\ud750\ud750 \uad6c\uba4d \uc22d\uc22d \uc2dc\uc6d0\ud558\uaca0\ub124\uc694.<\/span><\/div>
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\ubb50 \uc5ec\ud558\uac04 mode\uac00 \ubc14\ub00c\uba74 \uc4f0\uc774\ub294 Register\uac00 \ubc14\ub010\ub2e4\ub294 \uc0ac\uc2e4\ub9cc \uc54c\uba74 \ub429\ub2c8\ub2e4.  \u314b\u314b<\/span>
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\ubb50 \uc608\ub97c \ub4e4\uba74 \ub2e4\uc74c\ucc98\ub7fc \ub4e4 \uc218 \uc788\uaca0\ub124\uc694.<\/span><\/div>

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SVC mode\ub85c \ub3cc\ub2e4\uac00 Fast Interrupt\uac00 \uac78\ub824\uc11c FIQ mode\ub85c \uc9c4\uc785\ud588\uc744 \uacbd\uc6b0\uc758 Register\uc0c1\ud0dc\ub294<\/span><\/div>
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\uc778 \uac8c\uc9c0\uc694. \uc6b0\ud6c4\ud6c4~ \ubb50 \uad1c\ucc2e\uc544 \ubcf4\uc5ec\uc694?<\/span>
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\uc815\ub9ac\ud558\uba74, \ubaa8\ub4e0 mode\uac00 \uacf5\uc720\ud558\ub294 Register\ub294 CPSR, PC, R0~R7\uae4c\uc9c0\ub294 \ubaa8\ub450\uac00 \uacf5\uc720\ud569\ub2c8\ub2e4. \ub2e4\ub978 \ub9d0\ub85c\ub294 CPSR, PC, R0~R7\uae4c\uc9c0\ub294 ARM core\uc548\uc5d0 \ud55c \uac1c\uc529 \ubc16\uc5d0 \uc5c6\ub2e4~ \uc774\uac70\uc9c0\uc694.<\/span><\/div>

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\ub610 \ud2b9\uc774\ud55c \uc0ac\ud56d \ud558\ub098\ub294, System mode\uc640 User mode\ub294 \uc644\uc804\ud788 \ub611\uac19\uc740 register set\uc744 \uc4f4\ub2e4\ub294 \uac70\uc5d0\uc694. R0~R15, CPSR\uc744 \ubaa8\ub450 \uac19\uc774 \uc4f0\uba70 \ub531 \ud558\ub098\uc758 \ucc28\uc774\ub294 CPSR mode bits\uc758 \uac12\ub9cc\uc774 \ucc28\uc774\uac00 \ub0a9\ub2c8\ub2e4. \uc5ec\uae30\uc11c \uc8fc\ubaa9\ud560 \uc810\uc740 \uc65c System mode\ub294 SPSR\uc774 \uc5c6\ub290\ub0d0 \ud558\ub294 \ubb38\uc81c\uc778\ub370, \uc798 \uc0dd\uac01\ud574 \ubcf4\uc138\uc694. \uacc4\uc18d \uc990\uaca8\ubcfc Exception\uc5d0 \uadf8 \ud574\ub2f5\uc774 \uc788\uc2b5\ub2c8\ub2e4.<\/span><\/div>

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\uc774\ub807\uac8c \uc598\uae30 \ud558\ub2e4 \ubcf4\ub2c8, CPSR\uc774\ub77c\ub294 Register\uc758 \uc815\uccb4\uac00 \ud070 \uc5ed\ud560\uc744 \ud558\ub294 \ubaa8\uc591\uc778\ub370, \uc774 \ub140\uc11d\uc758 \uc815\uccb4\ub97c \uc0b4\ud3b4 \ubd10\uc57c \ud558\uaca0\uc0ac\uc635\ub2c8\ub2e4. \ub3c4\ub300\uccb4 CPSR, CPSR\ud558\ub294\ub370 \ub3c4\ub300\uccb4 \uc774\ub188\uc740 \ubb50 \ud558\ub294 \ub118 \uc774\ub0d0. CPSR\uc740 \ud2b9\ubcc4\ud55c Register \uc785\ub2c8\ub2e4. \ud2b9\ubcc4\ud55c \uc6a9\ub3c4\uc758 Register\ub4e4\uc740 CPSR, SPSR, R15 (PC), R14 (LR), R13 (SP)\uac00 \uc788\uc5b4\uc694. \ubb50, \uadf8\uac83\ub4e4\uc744 \ud558\ub098 \ud558\ub098 \ub72f\uc5b4 \uba39\uc5b4 \ubcf4\uba74...<\/span><\/div>

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CPSR\uc740 \uc57d\uc790\ub97c \ud480\uc5b4 \ub193\uc73c\uba74 Current Program Status Register\uac00 \uadf8 \uc815\uccb4\uc774\uace0\uc694. \uadf8 \ubaa8\uc591\uc0c8\ub294<\/span><\/div>
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\uc774\uc5d0\uc694.<\/span>
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32bit register\uc774\uace0\uc694. \uc55e\uc5d0 NZCV\ub294 Flag field\ub77c\uace0 \ud574\uc11c, \ubb54\uac00 \uc5f0\uc0b0\ud55c \ud6c4\uc5d0 set\ub418\ub294 register\uc785\ub2c8\ub2e4.<\/span><\/div>
\uc774 field\ub294 \ubc29\uae08 \ucc98\ub9ac\ub41c \uc5f0\uc0b0 \uacb0\uacfc\uc758 \uc0c1\ud0dc\ub97c \ub098\ud0c0\ub0b4\uc694.<\/span><\/div>

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1) N : Negative : \uc5f0\uc0b0\uacb0\uacfc\uac00 \ub9c8\uc774\ub108\uc2a4\uc778 \uacbd\uc6b0\uc5d0 set\ub429\ub2c8\ub2e4.<\/span><\/div>
2) Z : Zero : \uc5f0\uc0b0\uacb0\uacfc\uac00 0\uc778 \uacbd\uc6b0\uc5d0 set\ub418\uc694.<\/span><\/div>
3) C : Carry : \uc5f0\uc0b0\uacb0\uacfc\uc5d0 \uc790\ub9ac \uc62c\ub9bc\uc774 \ubc1c\uc0dd\ud55c \uacbd\uc6b0\uc5d0 set \ub429\ub2c8\ub2e4.<\/span><\/div>
4) V : oVer flow : \uc5f0\uc0b0\uc758 \uacb0\uacfc\uac00 overflow \ub0ac\uc744 \uacbd\uc6b0\uc5d0 set\ub418\ub294\ub370, Over flow\ub77c\ub294\uac74 \ub118\uce58\ub294 \uacbd\uc6b0\ub2c8\uae4c<\/span><\/div>
                            \uc6d0\ub798 \uac00\uc838\uc57c \ud558\ub294 Range\ubcf4\ub2e4 \uacb0\uacfc \uac12\uc774 \ud070 \uacbd\uc6b0\uac00 \uadf8 \uacbd\uc6b0\uc5d0 \ud574\ub2f9\ub429\ub2c8\ub2e4.<\/span><\/div>
\uc774\uac83\uc758 \ud544\uc694\uc131\uc740 ARM\uc758 \ucca0\ud559\uc774\uae30\ub3c4 \ud55c\ub370, ARM Assembly section\uc5d0\uc11c \ub610 \ub2e4\ub8e8\uae30\ub294 \ud558\uaca0\uc9c0\ub9cc,<\/span><\/div>
ARM core\ub294 Opcode\ub97c Memory\uc5d0\uc11c \uac00\uc838\uc624\uc790 \ub9c8\uc790 (Fetch) \uc774\ub97c \ubb34\uc870\uac74 \uc2e4\ud589\ud558\ub294 \uac83\uc774 \uc544\ub2c8\ub77c<\/span><\/div>
condition flag\uc778 NZCV\ub97c \ubcf4\uace0 \ubc14\ub85c \uc55e opcode\uc758 \uc2e4\ud589\uacb0\uacfc\ub97c \ubcf4\uace0 \uc2e4\ud589\ud560\uc9c0 \ub9d0\uc9c0\ub97c<\/span><\/div>
\uacb0\uc815\ud560 \uc218 \uc788\uc5b4\uc694. Default\ub294 AL \"Always\" , condition\uacfc \uad00\uac8c\uc5c6\uc774 \ud56d\uc0c1 \uc2e4\ud589 \uc774\uae34 \ud558\uc9c0\ub9cc\uc694.<\/span><\/div>
\ub4a4\ucabd\uc5d0 IF\ub294 IRQ\ub098 FIQ\uac00 \uac78\ub9b4 \uc218 \uc788\ub294\uc9c0\uc5d0 \uad00\ub828\ud55c field\ub85c\uc11c, 7\ubc88\uc9f8 bit\ub294 IRQ, 6\ubc88\uc9f8 bit\ub294 FIQ<\/span><\/div>
Enable\/ Disable\uc744 \ub098\ud0c0\ub0b4\ub294 fiied\uc785\ub2c8\ub2e4. 1\ub85c set\ud558\uba74 Disable, 0\uc73c\ub85c set\ud558\uba74 enable\uc774\uc8e0.<\/span><\/div>
\uc774\uac78\ub85c Interrupt\uac00 \uac78\ub9ac\uc9c0 \uc54a\ub3c4\ub85d control\uac00\ub2a5\ud569\ub2c8\ub2e4.<\/span><\/div>

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5\ubc88\uc9f8 T \ub294 Thumb mode\uc774\ub0d0, ARM mode\uc774\ub0d0\ub97c \ub098\ud0c0\ub0b4\ub294 field\ub85c\uc11c, ARM\/ Thumb mode\ub294<\/span><\/div>
ARM Thumb mode section\uc5d0\uc11c \uc790\uc138\ud788 \ub2e4\ub8e8\ub2c8\uae4c \ub108\ubb34 \uae09\ud558\uac8c \uc0dd\uac01 \uc548\ud558\uc154\ub3c4 \ub418\uc694.<\/span><\/div>

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0~4\uc758 5\uac1c bit\ub294 \ud604\uc7ac\uc758 mode\ub97c \ub098\ud0c0\ub0b4\ub294\ub370,<\/span><\/div>
\ud604\uc7ac SVC\uc778\uc9c0, UND \uc778\uc9c0, ABT \uc778\uc9c0\ub4f1\uc744 \ub098\ud0c0\ub0c5\ub2c8\ub2e4. \uc774 register\uac00 \ubc14\ub85c \ud604\uc7ac CPU\uc758 \uc0c1\ud0dc<\/span><\/div>
\ub97c \ub098\ud0c0\ub098\uaca0\uc8e0. \uc544~\uc8fc \uc911\uc694\ud55c register\uc785\ub2c8\ub2e4.<\/span><\/div>

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\uadf8\ub7ec\ub2c8\uae4c, CPSR\uc758 \uac12\uc740 \ud604\uc7ac\uc758 mode\ub3c4 \ud655\uc778 \uac00\ub2a5\ud55c register \uc778\uac70\uc8e0.<\/span><\/div>
\uc2e4\uc740 CPSR\uc758 \ud558\uc704 5bit\ub97c \uc6d0\ud558\ub294 mode\ub85c setting\ud558\uba74 \uadf8 mode\ub85c \uc804\ud658\ub3c4 \ub429\ub2c8\ub2e4.<\/span><\/div>
System mode\uc640 User mode\ub294 \uc774 CPSR\uc758 mode bit\ub9cc \ucc28\uc774\uac00 \ub098\uace0 \ub098\uba38\uc9c0 Register\ub294<\/span><\/div>
\ubaa8\ub450 \uac19\uc774 \uc0ac\uc6a9\ud569\ub2c8\ub2e4. \ub9c8\uce58 \ubd80\ubd80\ucc98\ub7fc \ud55c \ubab8\uc785\ub2c8\ub2e4. *^^* \ubd80\ub044.<\/span><\/div>

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\uc5ec\uae30\uc11c, SPSR\uc740 \ub610 \ubb50\ub0d0, Saved Program Status Register\uc785\ub2c8\ub2e4.<\/span><\/div>
SPSR\uc740 \ub9d0 \uadf8\ub300\ub85c CPSR\uc744 \ubcf5\uc0ac\ud574 \ub123\ub294 \ud2b9\uc218 Register\uc774\uc9c0\uc694. \uadf8\ub7fc \uc5b8\uc81c \uc368\uba39\ub290\ub0d0? CPSR\uc744<\/span><\/div>
backup \ud560 \ub54c \uc368\uba39\uc9c0\uc694. \uadf8\ub7fc \uc5b8\uc81c backup\ud558\ub290\ub0d0? SPSR\uc5d0 CPSR\uc758 \uac12\uc744 backup\ud574 \ub193\uace0<\/span><\/div>
mode\ub97c \ubc14\uafb8\uac8c \ub418\uc5c8\uc744 \ub54c, SPSR\uc758 \uac12\uc744 CPSR\uc5d0 \ub2e4\uc2dc \uc9d1\uc5b4 \ub123\uc73c\uba74 \uc774\uc804 mode\ub85c<\/span><\/div>
\uace7\ubc14\ub85c \ubcf5\uadc0\ud560 \uc218 \uc788\ub2e4\ub294 \uac83\uc774\uc9c0\uc694!<\/span><\/div>

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R14 (Linked Register)\ub294 \ub610 \ubb50\ub0d0. \ubcc4\uac70 \uc544\ub2d9\ub2c8\ub2e4\uc694. ARM\uc740 \uc5b4\ub518\uac00\ub85c branch (jump)\ub97c \ud560 \ub54c<\/span><\/div>
\uc5b4\ub514\uc11c branch \ud574 \uc654\ub294\uc9c0\ub97c \ud45c\uc2dc\ud574 \ub461\ub2c8\ub2e4. \ud5e8\uc824\uacfc \uadf8\ub798\ud154\ucc98\ub7fc \ube75\uac00\ub8e8\ub97c \ud758\ub824\ub450\ub294 \uc6a9\ub3c4\ub85c \uc0ac\uc6a9\ud558\ub294<\/span><\/div>
\uac70\uc5d0\uc694. \uadf8\ub807\uac8c \ud558\uba74 \ud568\uc218 \uac19\uc740\uac70 \ubd88\ub800\uc744 \ub54c \ub098\uc911\uc5d0 \uc5b4\ub514\ub85c \ub3cc\uc544\uac00\uc57c \ud560\uc9c0 LR\ub9cc \ubcf4\uba74 \ub3cc\uc544 \uac08 \uc218 \uc788\uaca0\uc8e0?<\/span><\/div>
\uc73c\ud750\ud750.<\/span><\/div>

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R13 (Stack Pointer)\ub294 \ud604\uc7ac Stack\uc744 \uc5b4\ub514\uae4c\uc9c0 \uc313\uc544 \ub450\uc5c8\ub294\uc9c0\ub97c \uac00\ub974\ud0b5\ub2c8\ub2e4.<\/span><\/div>
\uc774 \uc774\uc57c\uadf8\ub294 \ub098\uc911\uc5d0 Stack\uc5d0 \ub300\ud55c \uc18c\uace0\ud558\uace0\uc694, \ud568\uc218\uc758 \uad6c\uc870 \ubb50 \uc774\ub7f0\ub370\uc11c \ub354 \uc790\uc138\ud788 \ud3ed\ub85c\ud560 \uc608\uc815\uc778\ub370,<\/span><\/div>
\uc5b4\uca0c\uac70\ub098, Stack Pointer\uac00 \uc788\uc73c\ubbc0\ub85c \ud574\uc11c \ub9ce\uc740 \uac83\ub4e4\uc774 \uac00\ub2a5\ud558\uac8c \ub41c\uac70\uc8e0.<\/span><\/div>

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R15 (Program counter) \uc774 \ub140\uc11d\uc740 \ud604\uc7ac \uc5b4\ub514\ub97c \uc218\ud589\ud558\uace0 \uc788\ub294 \uac74\uc9c0\ub97c \ub098\ud0c0\ub0b4\ub294 \uac70\uc5d0\uc694.<\/span><\/div>
\ud655\uc7a5 to the CPU\uc5d0\uc11c\ub3c4 \ubcf4\uc558\uaca0\uc9c0\ub9cc, \ud604\uc7ac Instruction\uc744 Fetch\ud574 \uc628 \uc704\uce58\ub97c \uac00\ub9ac\ud0a4\uace0 \uc788\uc5b4\uc694. \uc694\uac70 \uc911\uc694\ud55c \uc0ac\uc2e4\uc774\ub2c8\uae4c \uc798 \uae30\uc5b5\ud574 \ub450\uc138\uc694. \uc2e4\ud589\ud558\ub294 \uc704\uce58\uac00 \uc544\ub2c8\ub77c Fetch\ud574\uc628 \uc704\uce58\ub97c \uac00\ub9ac\ud0a4\ub294 \uac70\ub2e4~ \uadf8\uac70\uc8e0.<\/span><\/div>

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\ub098\uba38\uc9c0 R0~R12\uae4c\uc9c0\ub294 CPU\uc758 \ub3d9\uc791\uc911\uc758 \uc800\uc7a5\uc6a9\ub3c4\ub85c \uc801\uc808\ud788 \uc0ac\uc6a9\ub418\ub294 \uac70\uc9c0\uc694. \uadf8\ub798\uc11c R0~R12\uae4c\uc9c0\ub294 \uc801\ub2f9\ud788 Register\ub77c\uace0 \ubd80\ub974\uace0, R13~R15, CPSR, SPSR\uc740 \ud2b9\ubcc4\ud55c \uc6a9\ub3c4\uac00 \uc788\ub2e4\uace0 \ud558\uc5ec, Special Purpose Register\ub77c\uace0 \uae4c\uc9c0 \uad6c\ubd84\ud574\uc694. \ucddf.<\/span><\/div>

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Register \uc598\uae30\ub97c \uaebc\ub0b4\uace0 \ub098\ub2c8, Context\ub77c\ub294 \uac70\uc5d0 \ub300\ud574\uc11c \uc815\uc758\ub97c \ub0b4\ub9ac\uace0 \uac00\uc57c\uaca0\uc2b5\ub2c8\ub2e4. \uc774 Context\ub77c\ub294 \uac8c \uc0c1\ub2f9\ud788 \uc911\uc694\ud55c \uc598\uae30\uac70\ub4e0\uc694. Context\ub97c \ubb38\ub9e5\uc774\ub77c\uace0\ub4e4 \ub9ce\uc774 \ub4e4 \ubc88\uc5ed\ud574 \ub193\uc558\ub294\ub370, \ub108\ubb34 \uc5b4\ub835\uc8e0. \uc800\ub294 Context\ub77c\ub294 \ub9d0\uc744 \ucc98\uc74c \uc811\ud588\uc744 \ub54c \ub3c4\ub300\uccb4 \uc774\uac8c \ubb34\uc2e0 \uc18c\ub9b0\uac00 \ud588\ub294\ub370 \uc774\uc81c\uc11c\uc57c \ucc38\uc73c\ub85c \uc801\ub2f9\ud558\uace0 \ucca0\ud559\uc801\uc778 \ub9d0\uc774\uad6c\ub098 \ud558\uace0 \ubb34\ub98e\uc744 \ud0c1 \uce60 \ub54c\ub3c4 \uc788\uae34 \ud558\uac70\ub4e0\uc694. Context Switching\uc744 \ubb38\ub9e5\uc804\ud658 \uc774\ub77c\ub294 \ub465 \ud574\uc11c \ud45c\ud604\ud574 \ub193\uc558\ub294\ub370, \ub108\ubb34 \uc5b4\ub835\ub354\ub780 \ub9d0\uc774\uc8e0.<\/span><\/div>

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\uadf8\ub798\uc11c \uc81c\uac00 \uace0\uc2ec\ud55c \ub05d\uc5d0 \ub354 \uc26c\uc6b4 \ub9d0\uc740 \uc5c6\uc744\uae4c~ \ud574\uc11c \uc774\ub807\uac8c \ud45c\ud604\uc744 \ud558\uace0 \uc0bd\ub2c8\ub2e4. \"\uc0c1\ud669\"<\/span><\/div>

<\/div>
Context\ub77c\ub294 \uac74 MCU\uc758 \ud604\uc7ac \uc0c1\ud669, Context Switching\uc774\ub77c\ub294 \uac74 \uc0c1\ud669\uc744 \ubc14\uafd4 \uce68.  \ubb50 \uadf8\ub7f0 \uac70\uc8e0. \uadf8\ub7fc \uadf8 \uc0c1\ud669\uc774\ub77c\ub294 \uac74 \ubb50\ub0d0.<\/span><\/div>

<\/div>
\uc911\ub300\uc7a5 : \uadf8 \ucabd \uc0c1\ud669\uc740 \uc5b4\ub54c?<\/span><\/div>
\uc774\ub4f1\ubcd1 : \ud604\uc7ac \uae40\ubcd1\uc7a5\ub2d8\uc740 \uc57c\uc2dd \uba39\uace0 \ub625 \uc2f8\ub7ec \uac00\uc168\uace0, \uc800\ub294 \ubcf4\ucd08\ub97c \uc798 \uc11c\uace0 \uc788\uc2b5\ub2c8\ub2e4. \uc774\uc0c1 \ubb34.<\/span><\/div>
\uc911\ub300\uc7a5 : OK \uc54c\uaca0\ub2e4.<\/span><\/div>

<\/div>
\uc774\ub807\ub4ef\uc774 \ubaa8\ub4e0 \uac83\uc744 \uc885\ud569\ud55c \uc0c1\ud0dc\ub97c \ub9d0\ud558\uc8e0. \uadf8\ub7fc \uc774\ub7f0 Software\uc5d0\uc11c\uc758 \uc0c1\ud669\uc740 \ubb50\ub0d0?<\/span><\/div>

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\ubc14\ub85c Register Set\uc758 Snap Shot\uc785\ub2c8\ub2e4. \uadf8\ub7ec\ub2c8\uae4c R0~R15, CPSR\uc758 \uac12\ub4e4\uc774 \ud604\uc7ac \uc0c1\ud669\uc774\uc8e0. \uc5b4\ub290 \uc21c\uac04\uc5d0 \ucc30\uce75 \ud558\uace0 Register\uc5d0 \ub4e4\uc5b4 \uc788\ub294 \uac12\ub4e4\uc744 \uc0ac\uc9c4 \ucc0d\ub294 \uac70\uc5d0\uc694. \uc774 \uac12\ub4e4\ub9cc \uc788\uc73c\uba74 \ud604\uc7ac MCU\uac00 \ubb58 \ud558\ub824\uace0 \ud588\uc5c8\ub294\uc9c0, \ubb58 \ud558\uace0 \uc788\uc5c8\ub294\uc9c0, \ubb58 \ud588\ub294\uc9c0 \ub4f1\ub4f1\uc744 \ub2e4 \ud30c\uc545\ud560 \uc218 \uc788\uc2b5\ub2c8\ub2e4.<\/span><\/div>

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\uc774 \ub9d0\uc740~ \ub2e4\ub978 \uc77c\uc744 \ud558\ub354\ub77c\ub3c4 \ud2b9\uc815\uc21c\uac04\uc5d0 \uc800\uc7a5\ud588\ub358 Context\ub97c \ub2e4\uc2dc \ubcf5\uc6d0\ub9cc \ud574\uc904 \uc218 \uc788\ub2e4\uba74 \uadf8 \ud2b9\uc815\uc21c\uac04\uc73c\ub85c \ub3cc\uc544\uac08 \uc218 \uc788\ub2e4~ \ub294 \ub9d0\uc785\ub2c8\ub2e4. \uadf8 \uc0c1\ud669\uc744 \uc7ac\ud604\ud55c\ub2e4\uace0\ub3c4 \ub9d0\ud560 \uc218 \uc788\uaca0\uc8e0.<\/span><\/div>

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\uacb0\uad6d\uc5d4 \uc544\ub798 Register \ud55c \uc904\uc774 Context\ub77c\uace0 \ubcf4\ubbc4 \ub429\ub2c8\ub2e4. \uc5b4\ub290 \uc21c\uac04\uc774\ub4e0 \uc544\ub798\uc758 Register set\uc744 \uc774\uc6a9\ud574\uc11c MCU\uac00 \ub3d9\uc791\ud558\uace0 \uc788\uaca0\uc8e0?<\/span><\/div>
\"5.jpg\"\r\n<\/span>

<\ub098\ub294 context><\/span>
<\/p>\r\n<\/div>


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\uc644\uc804 \uadf8\ub9bc\uc774 \uc7ac\ud0d5 \uc0bc\ud0d5 \uc774\ub124\uc694. \u314b\u314b.<\/span><\/div>
\uc694\ub188\uc758 Context\ub77c\ub294 \uac1c\ub150\uc744 \uc54c\uace0 \uc788\uc73c\uba74 \uc5b4\ub290 Processor\uc5d0\ub098 \ub4e4\uc774\ub308 \uc218 \uc788\uc2b5\ub2c8\ub2e4.<\/span><\/div>
\uc65c? \uc5b4\ub290 Processor\uac74 \uac04\uc5d0 \uc5b4\ub290 \uc21c\uac04\uc5d0\uac74 \uc774\ub7f0 Register set\uc744 \uc774\uc6a9\ud574\uc11c \ubb54\uac00 \ud558\uace0 \uc788\uc73c\ub2c8\uae4c\uc694.<\/span><\/div>

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 R8~R12\ub294 \uc65c \uc0c9\uae54\uc774 \ub2e4\ub978\uac00\uc694?<\/span><\/div>
   \ub4a4\uc5d0 \ub098\uc624\uaca0\uc9c0\ub9cc ARM, Thumb mode\uc758 \ucc28\uc774\uac00 \uadf8 \ub2f5\uc785\ub2c8\ub2e4. Thumb mode\ub294 R0~R7\ub9cc \uc4f0\uace0 ARM mode\ub294 R0~R12\uae4c\uc9c0 \ubaa8\ub450 \uc501\ub2c8\ub2e4. (R13, R14\ub294 ARM\/ Thumb\uc5d0 \uc0c1\uad00\uc5c6\uc774 \ubaa8\ub450 \uc4f0\uc5ec\uc694)<\/span><\/div>

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 \uc65c FIQ\ub294 banked register\uac00 \ub0a8\ub4e4\ubcf4\ub2e4 \ub9ce\uc744\uae4c\uc694?<\/span><\/div>
   \uadf8\uac83\uc774 mode\uac00 \uc788\ub294 \uc774\uc720 \uc911\uc5d0 \ud558\ub098 \uc785\uc8e0. \uc5ec\ub7ec \uac00\uc9c0 \uc6a9\ub3c4\uc758 \ub2e4\ub978 mode\ub85c\uc758 \uc804\ud658 \uc2dc\uc5d0 \uad73\uc774 stack\uc5d0 register backup\uc744 \ud558\ub098\ub77c\ub3c4 \ub35c\ud558\uba74 \uc2dc\uac04 \uc808\uc57d\uc774 \ub418\uaca0\uc2b5\ub2c8\ub2e4. \uadf8\ub7f0 \uc774\uc720\uc5d0\uc11c FAST!!! IRQ mode\ub85c\uc758 \uc804\ud658\uc740 \ub354\uc6b1 \ube60\ub974\uac8c \ub418\uc5b4\uc57c \ud558\ub2c8\uae4c, \uc804\uc6a9 register\ub97c \ud558\ub098\ub77c\ub3c4 \ub354 \ub454\uac70\uc8e0.<\/span><\/div><\/font><\/div>

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\u25a0 ARM \uc5b4\uc148\ube14\ub9ac\uc5b4 \uba85\ub839\uc5b4 \uc815\ub9ac<\/span><\/strong>
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\u203b \uc6a9\uc5b4 \uc815\uc758<\/span><\/div>
    <\/span> <\/span>Rd<\/span>: Destination Register   \/   <\/span>Rn<\/span>: Operand1 Register   \/  <\/span> <\/span>Rm<\/span>: Operand2 Register<\/span><\/div>
     <cond>: Execution Condition code<\/span><\/div>
     <S>: S-Suffix - Status Update Suffix - SPSR\uc758 \uac12\uc744 CPSR\ub85c \ubd88\ub7ec\uc640\uc11c Status\ub97c Update<\/span><\/div>
     <!> : ! - Suffix - Writeback Suffix - [,]\ub0b4\uc758 \uc120\ucc98\ub9ac \uc5f0\uc0b0 \uc218\ud589 \ud6c4 \uac12\uc744 \uac31\uc2e0<\/span><\/div>
     <Operand2>: Operand2\uac00 \uac00\uc9c8 \uc218 \uc788\ub294 \ud615\uc2dd<\/span><\/div>
          \u3131. #Immediate: 32bit  \uba85\ub839\uc5d0\uc11c Immediate\uac12\uc740 8-bit pattern\uc758 \uc9dd\uc218 shift \uac12 \ub9cc\uc744 \ud5c8\uc6a9<\/span><\/div>
          \u3134. Rm{, shift\uc5f0\uc0b0 #immediate}: Register(Rm)\uac12\uc5d0 #immediate \uac12\uc73c\ub85c Shift \uc5f0\uc0b0<\/span><\/div><\/font>
               <\/span><\/div>
                 \u00a7 Shift \uc5f0\uc0b0\uc758 \uc885\ub958<\/span><\/div>
               - asr(Arithmetic Shift Right): Immediate\uc758 \uac12 \ub9cc\ud07c right shift, \uc55e\uc5d0 bit\ub294 Sign Extension<\/span><\/div>
               - lsr(Logical Shift Right): Immediate\uc758 \uac12 \ub9cc\ud07c right shift, \uc55e\uc5d0 bit\ub294 0\uc73c\ub85c \ucc44\uc6c0<\/span><\/div>
               - lsl(Logical Shift Left): Immediate\uc758 \uac12 \ub9cc\ud07c left shift, \ub4a4\uc5d0 bit\ub294 0\uc73c\ub85c \ucc44\uc6c0<\/span><\/div>
               - ror(ROtate Right): Immediate\uc758 \uac12 \ub9cc\ud07c rotate right, rotate\ud6c4 bit 0\uac12\uc740 carry\uc5d0 \uc800\uc7a5<\/span><\/div>
               - rrx(Rotate Right eXtend): rrx\ub294 1bit \uc529 rotate right, bit 0\uac12\uc740 carry\uc5d0 \uc800\uc7a5<\/span><\/div><\/div><\/font>

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1. \ub370\uc774\ud130 \ucc98\ub9ac \uba85\ub839<\/span>(General Data Processing Instruction)<\/span><\/font><\/div><\/span><\/font>
     1.1 \uc0b0\uc220 \uc5f0\uc0b0<\/span><\/div>
Syntax<\/span><\/font>: add<cond><S> Rd, Rn, <Operand2><\/span><\/font><\/div><\/font>

<\/span><\/font><\/div>
          add: Rd := Rn + <Operand2><\/span> <\/span><\/div><\/font>
          sub: Rd := Rn - <Operand2><\/span><\/div><\/font>
          adc(ADd with Carry), sbc(SuBtract with Carry): Carry\ub97c \ud3ec\ud568\ud55c add, sub \uc5f0\uc0b0<\/span><\/div><\/font>
         <\/span><\/div><\/font>
          rsb(Reverse SuBtract): Rd := <Operand2> - Rn<\/span><\/div><\/font>
          rsc(Reverse Subract with Carry): Carry\ub97c \ud3ec\ud568\ud55c \uc5ed sub \uc5f0\uc0b0<\/span><\/div><\/font>

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     <\/span><\/font>1.2 \ub17c\ub9ac \uc5f0\uc0b0<\/span><\/div><\/font>
Syntax: and<cond><S> Rd, Rn, <Operand2><\/span><\/font><\/div><\/font>

<\/div>
          and: Rd := Rn & <Operand2><\/span><\/div><\/font>
          orr:  Rd := Rn | <Operand2><\/span><\/div><\/font>
          eor: Rd := Rn ^ <Operand2><\/span><\/div><\/font>
          bic: Rd := Rn & !<Operand2><\/span><\/div><\/font><\/div><\/div>
     1.3 Register \uac12 \uc800\uc7a5<\/span><\/div>
Syntax: mov<cond><S> Rd, <Operand2><\/span><\/div>

<\/span><\/font><\/div>
          mov: Rd := <Operand2><\/span><\/div><\/font>
          mvn: Rd := !<Operand2><\/span><\/div><\/font>

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     <\/span><\/font>1.4 \ube44\uad50<\/span><\/div><\/font>
Syntax: cmp<cond><S> Rn, <Operand2><\/span><\/div>

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          cmp: Rn\uac12\uc5d0\uc11c Opeand2\uac12\uc744 \ube7c\uc11c \uadf8 \uacb0\uacfc\ub97c Status flag\uc5d0 \ubc18\uc601, SUBS\uc640 \ub3d9\uc77c\ud55c \uba85\ub839<\/span><\/div><\/font>
          cmn: Rn\uac12\uc5d0\uc11c Operand2\uac12\uc744 \ub354\ud574\uc11c \uadf8 \uacb0\uacfc\ub97c Status flag\uc5d0 \ubc18\uc601, ADDS\uc640 \ub3d9\uc77c\ud55c \uba85\ub839<\/span><\/div><\/font>

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          tst: Rn\uacfc Opearand2\ub97c bit and \uc5f0\uc0b0\uc744 \uc218\ud589\ud574\uc11c \uadf8 \uacb0\uacfc\ub97c Status flag\uc5d0 \ubc18\uc601, ANDS\uc640 \ub3d9\uc77c\ud55c \uba85\ub839<\/span><\/div><\/font>
          teq: Rn\uacfc Operand2\ub97c bit xor \uc5f0\uc0b0\uc744 \uc218\ud589\ud574\uc11c \uadf8 \uacb0\uacfc\ub97c Status flag\uc5d0 \ubc18\uc601, EORS\uc640 \ub3d9\uc77c\ud55c \uba85\ub839<\/span><\/div><\/font>

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2. \uba54\ubaa8\ub9ac \uc811\uadfc \uba85\ub839<\/span>(Memory Accesss Instruction)<\/span><\/font><\/div><\/font>

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          <\/span><\/font>Syntax<\/span>: ldr<cond><B> Rd, label<\/span><\/font><\/div><\/font>
                       ldr<cond><B><T> Rd, [Rn]<\/span><\/div><\/font>
                       ldr<cond><B> Rd, [Rn, FlexOffset]<!>         ;Pre-Indexed<Auto-Indexing><\/span><\/div><\/font>
                       ldr<cond><B><T> Rd, [Rn], FlexOffset        ;Post-Indexed<\/span><\/div><\/font>

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          <<\/span><\/font>B<\/span>>: B Suffix\uac00 \uc788\uc744 \uacbd\uc6b0 8-bit Unsigned byte \ub2e8\uc704\ub85c Access, \uc5c6\uc744 \uacbd\uc6b0 32-bit word\ub85c Access<\/span><\/font><\/div><\/font>
          <<\/span><\/font>T<\/span>>: T suffix\uac00 \uc788\uc744 \uacbd\uc6b0 Processor\uac00 User mode\uc5d0\uc11c memory access \ucc98\ub9ac<\/span><\/font><\/div><\/font>
          <\/span><\/font>FlexOffset<\/span>:<\/span><\/font><\/div><\/font>
               \u3131.#Immediate: -4095 \ubd80\ud130 -4096\uc0ac\uc774\uc758 \uc0c1\uc218 \uac12<\/span><\/div><\/font>
               \u3134.{-}Rm{, shift\uc5f0\uc0b0}: Rm\uc740 \uc74c\uc758 \ubd80\ud638\ub97c \uac00\uc9c8 \uc218 \uc788\uc73c\uba70, Rm\uc758 Shift \uc5f0\uc0b0\ub3c4 \uac00\ub2a5\ud568<\/span><\/div><\/font>

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     <\/span><\/font>2.1 Load \ub610\ub294 Store \uba85\ub839 \uc608\uc81c<\/span><\/div><\/font>

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          ldr r0, [r1]: r1\uc5d0 \uc800\uc7a5\ub41c \uc8fc\uc18c\ub97c \uc774\uc6a9\ud574\uc11c \uba54\ubaa8\ub9ac\ub85c\ubd80\ud130 r0\ub85c \uac12\uc744 \ubd88\ub7ec\uc634<\/span><\/div><\/font>
          str r0, [r1], #4: r0\uc758 \uac12\uc744 \uba54\ubaa8\ub9ac\uc758 r1\uc758 \uc8fc\uc18c\uc5d0 \uc800\uc7a5\ud558\uace0 r1\uc744 +4\ud568.<\/span><\/div><\/font>
          \ucc38\uace0) \ubd80\ud638\uac00 \uc788\ub294 Halfword, Byte\ub85c \uc77d\uc744 \ub54c\ub294 SH(Signed Halfword), SB(Signed Byte) <--(ldr only)<\/span><\/div><\/font>
                  Unsigned Halfword\ub85c \uc77d\uac70\ub098 \uc800\uc7a5\ud560 \ub54c\ub294 H\ub97c \uc0ac\uc6a9.<\/span><\/div><\/font>
                  Doubleword\uc758 \uacbd\uc6b0 D \ub97c \uc0ac\uc6a9, \uc774 \ub54c\uc758 Offset\uc740 {-}Rm \ub9cc \ud5c8\uc6a9\ud568.<\/span><\/div><\/font>

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     <\/span><\/font>2.2 Multiple Load \ub610\ub294 Store \uba85\ub839<\/span><\/div><\/font>

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Syntax: ldm<cond><addrmode> Rn<!>, {reglist}<^><\/span><\/div><\/div>

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          <<\/span><\/font>addrmode<\/span>>: address mode\uc5d0\ub294 \ucd1d 8\uac00\uc9c0\uac00 \uc788\uc73c\uba70, 4\uac00\uc9c0\ub294 address\uc758 \uc5f0\uc0c1 \ubc29\uc2dd\uc5d0 \ub530\ub978<\/span><\/font><\/div><\/font>
                                \uad6c\ubd84\uc774\uba70 4\uac00\uc9c0\ub294 stack\uc758 \ud2b9\uc131\uc5d0 \ub530\ub978 \uad6c\ubd84\uc774\ub2e4.<\/span><\/div><\/font>
              - IA(Increment Address after each transfer), - IB(Increment Address after each transfer)<\/span><\/div><\/font>
              - DA(Decrement Address after each transfer), - DB(Decrement Address after each transfer)<\/span><\/div><\/font>

<\/div>
              - FD(Full descending stack): stack\uc758 \uc8fc\uc18c\uc5d0 data\uac00 \uc800\uc7a5\uc774 \ub41c \uc0c1\ud0dc\uc774\uace0, \uc8fc\uc18c\uac00 \uac10\uc18c\ud558\uba74\uc11c \uc800\uc7a5<\/span><\/div><\/font>
              - ED(Emtpy descending stack): stack\uc758 \uc8fc\uc18c\uc5d0 data\uac00 \uc5c6\ub294 \uc0c1\ud0dc\uc774\uace0, \uc8fc\uc18c\uac00 \uac10\uc18c\ud558\uba74\uc11c \uc800\uc7a5<\/span><\/div><\/font>
              - FA(Full ascending stack): stack\uc758 \uc8fc\uc18c\uc5d0 data\uac00 \uc800\uc7a5\uc774 \ub41c \uc0c1\ud0dc\uc774\uace0, \uc8fc\uc18c\uac00 \uc99d\uac00\ud558\uba74\uc11c \uc800\uc7a5<\/span><\/div><\/font>
              - EA(Emtpy ascending stack): stack\uc758 \uc8fc\uc18c\uc5d0 data\uac00 \uc5c6\ub294 \uc0c1\ud0dc\uc774\uace0, \uc8fc\uc18c\uac00 \uc99d\uac00\ud558\uba74\uc11c \uc800\uc7a5<\/span><\/div><\/font>

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          <<\/span><\/font>!<\/span>>: ! - Suffix\uac00 \uc788\uc744 \uacbd\uc6b0 \ub9c8\uc9c0\ub9c9 \uc8fc\uc18c(\ucd5c\uc885\uc73c\ub85c \uc774\ub3d9\ud55c \uc8fc\uc18c)\ub97c Rn\uc5d0 \uc800\uc7a5\ud568<\/span><\/font><\/div><\/font>
          <<\/span><\/font>^<\/span>>: SPSR\uc758 \uac12\uc744 CPSR\uc5d0 \ub123\uc5b4\uc90c, S-Suffix\uc640 \ub3d9\uc77c\ud55c \uae30\ub2a5\uc744 \uc218\ud589\ud568.<\/span><\/font><\/div><\/font>

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          ldm: Rn\uc73c\ub85c \ubd80\ud130 reglist\uc5d0 \uc9c0\uc815\ud55c register \uc218 \ub9cc\ud07c \uac12\uc744 \ubd88\ub7ec\uc634<\/span><\/div><\/font>
          stm: reglist\uc5d0 \uc788\ub294 register\uc758 \uac12\ub4e4\uc744 Rn\uc5d0 \uc800\uc7a5\ud568.<\/span><\/div><\/font>

<\/div>
          <\/span><\/font>[\uc8fc\uc758]<\/span><\/font> Reglist\uc5d0 \uc9c0\uc815\ud55c Register\uc758 \uc21c\uc11c\uc640 \uc0c1\uad00\uc5c6\uc774 Register\uc758 \ubc88\ud638\uac00 \ub0ae\uc740 \uac12\uc774<\/span><\/font><\/div><\/font>
                    \uba54\ubaa8\ub9ac\uc758 \ub0ae\uc740 \uc8fc\uc18c\uc5d0 \uc800\uc7a5 \ub610\ub294 \uc77d\uc5b4\uc9c4\ub2e4. reglist\ub294 'r1,r2,r3' \ub610\ub294 'r1-r3'\uc73c\ub85c \ud45c\ud604<\/span><\/div><\/font>
          <\/span><\/font>[\uc790\uc8fc \uc0ac\uc6a9\ub418\ub294 \ud615\uc2dd]<\/span><\/font> STMFD sp!, {r4-r7,lr} \/ LDMFD sp!, {r4-r7,pc}<\/span><\/font><\/div><\/font>

<\/div>
3. \ubd84\uae30 \uba85\ub839<\/span>(Branch Instruction)<\/span><\/font><\/div><\/font>

<\/span><\/font><\/div>
Syntax<\/span>: b<cond> label<\/span><\/font><\/div><\/span><\/div>

<\/div>
     b: label\uc774 \uc788\ub294 \uc8fc\uc18c\ub85c branch(PC\uac12\uc5d0 label\uc758 \uc8fc\uc18c\ub97c \uc785\ub825)<\/span><\/div><\/font>
     bl: \ub2e4\uc74c \uba85\ub839\uc758 \uc8fc\uc18c\ub97c lr\uc5d0 \uc800\uc7a5\ud558\uace0, b\uc640 \uac19\uc774 label\uc758 \uc8fc\uc18c\ub85c branch<\/span><\/div><\/font>

<\/div>
4. \uae30\ud0c0 \uba85\ub839\uc5b4<\/span><\/div><\/font>
     <\/span><\/font>4.1 Software Interrupt<\/span><\/div><\/font>
Syntax: swi<cond> Immediate_24bit<\/span><\/div>

<\/div>
          swi: \uc9c0\uc815\ud55c \ubc88\ud638\ub97c \uac16\ub294 Software Interrupt\ub97c \ubc1c\uc0dd\uc2dc\ud0b4, \ud574\ub2f9 \ubc88\ud638\uc5d0 \ub9de\ub294 SWI vector\ub85c branch<\/span><\/div><\/font>
               (Software Interrupt\uac00 \uac78\ub9ac\uba74 \ud504\ub85c\uc138\uc11c\uc758 \ubaa8\ub4dc\ub294 Supervisor\ub85c \ubcc0\uacbd\ub428)<\/span><\/div><\/font>

<\/div>
     <\/span><\/font>4.2 PSR Access<\/span><\/div><\/font>
Syntax: mrs<cond> Rd, psr<\/span><\/div>

<\/div>
                    psr\uc5d0 \uc9c0\uc815\ud55c \uac12(cpsr \ub610\ub294 spsr)\ub85c \ubd80\ud130 \uac12\uc744 \ubd88\ub7ec\uc640\uc11c Rd\uc5d0 \uc800\uc7a5 (Register <- PSR)<\/span><\/div><\/font>

<\/div>
Syntax: msr<cond> psr_(field), #Immediate_8bit<\/span><\/div>
msr<cond> psr_fields, Rm      <\/span><\/div>

<\/span><\/font><\/div>
                    Register(Rm)\uc758 \uac12 \ub610\ub294 8bit Immediate\uac12\uc744 psr(cpsr \ub610\ub294 spsr)\uc5d0 \uc800\uc7a5 (Register -> PSR)<\/span><\/div><\/font>
                    (field): f, s, x, c \uac12\uc774 \uc120\ud0dd\uc801\uc73c\ub85c \uc62c \uc218 \uc788\uc74c. \uc9c0\uc815\ud55c field \uc601\uc5ed\uc5d0\ub9cc \uac12\uc744 \uc800\uc7a5\ud568.<\/span><\/div><\/font>

<\/div>
          <\/span>[\uc8fc\uc758]<\/span><\/font> \ud504\ub85c\uc138\uc11c\uac00 User \ub610\ub294 System mode\uc77c \ub54c\ub294 SPSR\uc5d0 \uc5d1\uc138\uc2a4 \ud558\uc9c0 \ub9d0\uc544\uc57c \ud55c\ub2e4.<\/span><\/div>
          <\/span>[\uc790\uc8fc \uc0ac\uc6a9\ub418\ub294 \ud615\uc2dd]<\/span><\/font> msr CPSR_c,r0<\/span><\/div><\/div><\/div><\/font><\/span>
5. \uc0c1\ud0dc \ud50c\ub798\uadf8\uc640 \uc2e4\ud589 \uc870\uac74 \ucf54\ub4dc<\/span><\/font>(Status Flags & Execution Condition Codes)<\/span><\/font><\/span><\/div>
     N: \uc5f0\uc0b0 \uacb0\uacfc\uac00 \uc74c\uc758 \uac12\uc744 \uac00\uc9c8 \ub54c Set '1'<\/span><\/div>
     Z: \uc5f0\uc0b0 \uacb0\uacfc\uac00 \uc601\uc77c \ub54c Set '1'<\/span><\/div>
     C: \uc5f0\uc0b0 \uacb0\uacfc\uac00 \uce90\ub9ac(Carry)\ub97c \uac00\uc9c8 \ub54c Set '1'<\/span><\/div>
     V: \uc5f0\uc0b0 \uacb0\uacfc \uc624\ubc84\ud50c\ub85c\uc6b0(Overflow)\ub97c \ubc1c\uc0dd\uc2dc\ud0ac \ub54c Se<\/span><\/div><\/font><\/font>
\"tt.png\"\r\n


<\/p>\r\n<\/div><\/div><\/div><\/div><\/div>

<ARM Instructioin Set><\/span><\/div><\/font>
\"3577297971.png\"\r\n<\/span>


<\/p>\r\n<\/div>

     \u2460 opcode<cond><S> Rd, Rn, #Immediate<\/span><\/div><\/font>
     \u2461 opcode<cond><S> Rd, Rn, Rm OP #Imm<\/span><\/div><\/font>
     \u2462 opcode<cond><S> Rd, Rn, Rm OP Rs<\/span><\/div><\/font>
          - cmp, cmn \uba85\ub839\uc5d0\uc11c\ub294 Rd\ub294 \ubb34\uc870\uac74 '0' \uac12\uc744 \ub123\uc5b4\uc918\uc57c \ud568.(SBZ(Should Be Zero))<\/span><\/div><\/font>

<\/div>
     \u2463 opcode<cond> Rd, Rn, #Immediate<\/span><\/div><\/font>
     \u2464 opcode<cond> Rd, Rn, Rm OP #Imm<\/span><\/div><\/font>
     \u2465 opcode<cond> Rd, <address><\/span><\/div><\/font>
     \u2466 opcode<cond><addrmode> Rm, Register_List^<\/span><\/div><\/font>
     \u2467 opcode<cond><addrmode> Rm<!>, Register_List<\/span><\/div><\/font>
     \u2468 opcode<cond><addrmode> Rm<!>, Register_List^<\/span><\/div><\/font>
          - P='1' Pre, P='0' Post \/ U='1' Increment, U='0' Decrement \/ B='1' Byte load, B='0' Word load \/<\/span><\/div><\/font>
            W='1' Write-back(Auto-Index) W='0' \/ L='1' opcode\ub294 ldr, L= '0' str \/<\/span><\/div><\/font>
            I='1' Addr_mode\uac00 \ubaa8\ub450 Offset field I='0' \uc55e\uc5d0 Addr_mode\ub294 '0' \ub4a4\uc5d0 Addr_mode\ub294 Rm \/<\/span><\/div><\/font>
            S='1' Signed, S='0' Unsigned \/ H='1' Half Word, H='0' Word or Byte<\/span><\/div><\/font>

<\/div>
     \u2469 b<cond> #Target Address(24bit Offset) - L\uc758 \uac12\uc774 '1'\uc774\uba74 bl \uba85\ub839<\/span><\/div><\/font>

<\/div>
     \u246a SWI #SWI Number<\/span><\/div><\/font>

<\/div>
     \u246b mrs<cond><S> Rd, PSR<\/span><\/div><\/font>
     \u246c msr<cond><S> PSR_<Field_Mask>, Rm<\/span><\/div><\/font>
     \u246d msr<cond><S> PSR_f, #Immediate<\/span><\/div><\/font>
          - S\uc758 \uac12\uc774 '1'\uc774\uba74 SPSR\uc5d0\uc11c, '0'\uc774\uba74 CPSR.<\/span><\/div><\/font>
          - SBO(Should Be One) \uc601\uc5ed\uc740 '1'\ub85c, SBZ(Should Be Zero) \uc601\uc5ed\uc740 '0'\uc758 \uac12\uc744 \ub123\uc5b4\uc918\uc57c \ud568.<\/span><\/div>

<\/span><\/div>

<\/span><\/div>

<\/span><\/div>

<\/span><\/div>

<\/span><\/div>
\u25a0 \uc790\uc8fc \uc0ac\uc6a9\ub418\ub294 ARM \uc5b4\uc148\ube14\ub9ac \uba85\ub839\uc5b4 \uc694\uc57d<\/span><\/strong><\/span><\/div>

<\/div>
1. MOV<\/span><\/div>

<\/span><\/div>
ARM \uc5b4\uc148\ube14\ub9ac \uba85\ub839\uc5b4\ub294 MOV \uba85\ub839\uc5b4\uc640 \ub17c\ub9ac \ubc0f \uc0ac\uce59\uc5f0\uc0b0 \uba85\ub839\uc5b4\uc5d0 \ubaa8\ub450 \uc26c\ud504\ud2b8 \uc5f0\uc0b0\uc774<\/span><\/div>

<\/span><\/div>
\uac00\ub2a5\ud55c\ub370, \uc774\uac83\uc744 \ub098\ud0c0\ub0b4\ub294 \ud45c\uc9c0\uac00 \ub05d\uc5d0 \ubd99\uc744 \uc218 \uc788\ub2e4\ub294 \uac83\uc5d0 \uc720\uc758\ud55c\ub2e4.<\/span><\/div>

<\/span><\/div>
\uc26c\ud504\ud2b8 \uc5f0\uc0b0\uc5d0\ub294 ASR(\uc624\ub978\ucabd \uc26c\ud504\ud2b8, \ube48\uc790\ub9ac\ub294 \ubd80\ud638\uac00 \ub530\ub77c\uc634),<\/span><\/div>

<\/span><\/div>
LSR(\uc624\ub978\ucabd\uc73c\ub85c \uc26c\ud504\ud2b8, \ube48\uc790\ub9ac\ub294 0\uc73c\ub85c \ucc44\uc6cc\uc9d0),<\/span><\/div>

<\/span><\/div>
LSL(\uc67c\ucabd\uc73c\ub85c \uc26c\ud504\ud2b8, \ube48\uc790\ub9ac\ub294 0\uc73c\ub85c \ucc44\uc6cc\uc9d0),<\/span><\/div>

<\/span><\/div>
ROR(\uc624\ub978\ucabd\uc73c\ub85c rotation )<\/span><\/div>

<\/span><\/div>
\uc815\ub3c4\ub97c \uc54c\uc544\ub450\uba74 \uc720\uc6a9\ud558\ub2e4.<\/span><\/div>

<\/span><\/div>
\uc608)<\/span><\/div>

<\/span><\/div>
MOV r0, [r2,r4] ; r2+r4 \uc758 \uc8fc\uc18c\uc5d0 \uc788\ub294 \uac12\uc744 \uc77d\uc5b4\uc11c r0\uc5d0 \uc800\uc7a5\ud55c\ub2e4.<\/span><\/div>

<\/span><\/div>
MOV r1, r2, ROR #1 ; r2\ub97c \uc624\ub978\ucabd\uc73c\ub85c \ud55c \ube44\ud2b8\ub9cc\ud07c rotation \ud574\uc11c r1\uc5d0 \uc800\uc7a5<\/span><\/div>

<\/span><\/div>
2. ADD, SUB, AND, ORR<\/span><\/div>

<\/span><\/div>
\uc608)<\/span><\/div>

<\/span><\/div>
ADD r1, r2, #4 ; r2\uc5d0 4\ub97c \ub354\ud574\uc11c r1\uc5d0 \uc800\uc7a5<\/span><\/div>

<\/span><\/div>
SUB r1, r1, #1 ; r1\uc758 \uac12\uc744 \ud558\ub098 \uac10\uc18c<\/span><\/div>

<\/span><\/div>
ORR r4, r5, r7, LSR r2 ; r7\uc744 \uc624\ub978\ucabd\uc73c\ub85c \ub17c\ub9ac \uc26c\ud504\ud2b8\ub97c r2\ub9cc\ud07c \ud55c\ub2e4\uc74c \uadf8 \uacb0\uacfc\ub97c<\/span><\/div>

<\/span><\/div>
; r5\uc640 or \uc5f0\uc0b0\ud558\uc5ec r4\uc5d0 \uc800\uc7a5\ud55c\ub2e4.<\/span><\/div>

<\/span><\/div>
3. UMULL, SMULL<\/span><\/div>

<\/span><\/div>
\uacf1\ud558\uae30 \uc5f0\uc0b0\uc774\ub2e4. 32\ube44\ud2b8\uc9dc\ub9ac \ub450 \uac1c\ub97c \uacf1\ud558\uba74 64\ube44\ud2b8\uc9dc\ub9ac\uac00 \ub098\uc624\ubbc0\ub85c \uacb0\uacfc\uac12\uc744 \uc800\uc7a5\ud558\ub294<\/span><\/div>

<\/span><\/div>
\ub370 \ub450 \uac1c\uc758 \ub808\uc9c0\uc2a4\ud130\uac00 \ud544\uc694\ud558\ub2e4. \uacb0\uacfc \ub808\uc9c0\uc2a4\ud130\uc758 \uc704\uce58\uc5d0 \uc8fc\uc758\ud55c\ub2e4. UMULL\uc740 \ubd80\ud638\uac00<\/span><\/div>

<\/span><\/div>
\uc5c6\ub294 \uacf1\ud558\uae30\uc774\uace0, SMULL\uc740 \ubd80\ud638\uac00 \uc788\ub294 \uacf1\ud558\uae30 \uc774\ub2e4.<\/span><\/div>

<\/span><\/div>
\uc608)<\/span><\/div>

<\/span><\/div>
UMULL r4, r5, r1, r2 ; r1\uacfc r2\ub97c \uacf1\ud574\uc11c \uc0c1\uc704 32\ube44\ud2b8\ub294 r5\uc5d0 \uc800\uc7a5\ud558\uace0 \ud558\uc704 32\ube44\ud2b8\ub294<\/span><\/div>

<\/span><\/div>
; r4\uc5d0 \uc800\uc7a5\ud55c\ub2e4.<\/span><\/div>

<\/span><\/div>
5. B, BL, BNE, BEQ, CMP<\/span><\/div>

<\/span><\/div>
BL\uc740 \ubd84\uae30 \uba85\ub839\uc774\ub2e4.<\/span><\/div>

<\/span><\/div>
\uc608)<\/span><\/div>

<\/span><\/div>
B there ; \ub77c\ubca8\uc774 there\uc778 \uacf3\uc73c\ub85c \ubb34\uc870\uac74 \ubd84\uae30\ud55c\ub2e4.<\/span><\/div>

<\/span><\/div>
BL sub+ROM ; \uacc4\uc0b0\ub41c \uc704\uce58\uc758 \uc11c\ube0c\ub8e8\ud2f4\uc744 \ud638\ucd9c\ud55c\ub2e4.<\/span><\/div>

<\/span><\/div>
BNE(0\uc774 \uc544\ub2cc \uacbd\uc6b0 \ubd84\uae30)\uc640 BEQ(0\uc774\uba74 \ubd84\uae30) \ub294 branch \uba85\ub839\uc5b4\uc774\uace0 CMP\ub294 \ube44\uad50 \uba85\ub839<\/span><\/div>

<\/span><\/div>
\uc5b4\uc774\uc9c0\ub9cc \ub458\uc774 \uac19\uc774 \uc4f0\uc774\ub294 \uacbd\uc6b0\uac00 \ub9ce\uc73c\ubbc0\ub85c \ud55c\uaebc\ubc88\uc5d0 \uc124\uba85\ud55c\ub2e4.<\/span><\/div>

<\/span><\/div>
\uc608)<\/span><\/div>

<\/span><\/div>
CMP r1, #4 ; r1\uc774 4\uc774\uba74 \ud50c\ub798\uadf8\uac00 0\uc73c\ub85c \uc14b\ud305\ub41c\ub2e4.<\/span><\/div>

<\/span><\/div>
BEQ there ; \ud50c\ub798\uadf8\uac00 0\uc774\uba74 \ub77c\ubca8\uc774 there\uc778 \uacf3\uc73c\ub85c \ubd84\uae30\ud558\uace0, \uadf8\ub807\uc9c0 \uc54a\uc73c\uba74<\/span><\/div>

<\/span><\/div>
; \ub2e4\uc74c \uba85\ub839\uc5b4\uac00 \uc218\ud589\ub41c\ub2e4.<\/span><\/div>

<\/span><\/div>
6. LDR, STR<\/span><\/div>

<\/span><\/div>
LDR\uc740 load \uba85\ub839\uc774\ub2e4. LDR\uc5d0\ub294 \ubd88\ub7ec\uc624\ub294 \ubcc0\uc218\uc758 \ud06c\uae30\uc5d0 \ub530\ub77c LDRB, LDRH, LDR\uc758 \uc138<\/span><\/div>

<\/span><\/div>
\uac00\uc9c0 \uc885\ub958\uac00 \uc788\ub2e4. LDRB\ub294 byte \ubcc0\uc218\ub97c \ubd88\ub7ec\uc62c \ub54c, LDRH\ub294 short \ubcc0\uc218\ub97c \ubd88\ub7ec\uc62c \ub54c,<\/span><\/div>

<\/span><\/div>
LDR\uc740 int \ubcc0\uc218\ub97c \ubd88\uc5b4\uc62c \ub54c \uc4f4\ub2e4. STR\ub294 store \uba85\ub839\uc73c\ub85c \ub9c8\ucc2c\uac00\uc9c0\ub85c STRB, STRH, STR<\/span><\/div>

<\/span><\/div>
\uc774 \uc788\ub2e4.<\/span><\/div>

<\/span><\/div>
\uccab \ubc88\uc9f8 \uc778\uc790\ub294 \ub808\uc9c0\uc2a4\ud130\uac00 \ub450\ubc88 \uc9f8 \uc778\uc790\ub294 \uc8fc\uc18c\uac00 \ub41c\ub2e4. \uc138 \ubc88\uc9f8 \uc778\uc790\ub294 load\/store \uc5f0<\/span><\/div>

<\/span><\/div>
\uc0b0\uc744 \ud55c \ub2e4\uc74c \uc8fc\uc18c\uac12\uc744 \uc99d\uac00\uc2dc\ud0a4\uace0\uc790 \ud560 \ub54c, \uc5bc\ub9c8\ub9cc\ud07c \uc99d\uac00\uc2dc\ud0ac \uc9c0\ub97c \uc9c0\uc815\ud55c\ub2e4.<\/span><\/div>

<\/span><\/div>
\uc608)<\/span><\/div>

<\/span><\/div>
LDR r1, [r2, #16] ; r2\uc5d0 16 byte\ub9cc\ud07c \ub354\ud55c \uc8fc\uc18c\uc5d0\uc11c \uc815\uc218\ud615 \uac12\uc744 \uc77d\uc5b4\uc640 r1\uc5d0 \uc800\uc7a5\ud55c\ub2e4.<\/span><\/div>

<\/span><\/div>
STR r1, [r2], #4 ; r2\uc758 \uc8fc\uc18c\uc5d0 r1\uc744 \uc800\uc7a5\ud558\uace0 \ub09c \ud6c4, r2\ub97c 4\ub9cc\ud07c \uc99d\uac00\uc2dc\ud0a8\ub2e4.<\/span><\/div>

<\/span><\/div>
7. LDMFD, STMFD<\/span><\/div>

<\/span><\/div>
LDM\/STM\uc740 LDR\/STR\uc758 \ubcc0\uc885\uc73c\ub85c \ube14\ub85d \ub2e8\uc704\ub85c load\/store \ud560 \ub54c \uc0ac\uc6a9\ud55c\ub2e4. \uc911\uc694\ud55c \uc6a9\ub3c4<\/span><\/div>

<\/span><\/div>
\ub294 \uc2a4\ud0dd\uc5d0 \ub808\uc9c0\uc2a4\ud130 \uac12\uc744 \uc800\uc7a5\ud558\uac70\ub098 \ubcf5\uc6d0\ud558\ub294 \uac83\uc774\ub2e4. \uc65c\ub0d0\ud558\uba74 \uc2a4\ud0dd\uc5d0 \uc800\uc7a5\/\ubcf5\uc6d0\ud560 \ub54c<\/span><\/div>

<\/span><\/div>
\ub294 \uc5ec\ub7ec \uac1c\uc758 \ub808\uc9c0\uc2a4\ud130\ub97c \uc800\uc7a5\/\ubcf5\uc6d0\ud574\uc57c \ud558\uae30 \ub54c\ubb38\uc774\ub2e4.<\/span><\/div>

<\/span><\/div>
\uc2a4\ud0dd\uacfc \uad00\ub828\ud574\uc11c\ub294 LDMFD\/STMFD, LDMED\/STMED, LDMFA\/STMFA, LDMEA\/STMEA \ub4f1<\/span><\/div>

<\/span><\/div>
\uc774 \uc0ac\uc6a9\ub418\uace0, \uc2a4\ud0dd\uacfc \uad00\ub828\uc5c6\uc774 \uc0ac\uc6a9\ud560 \ub54c\ub294 LDMIA,LDMIB, LDMDA, LDMDB, STMIA,<\/span><\/div>

<\/span><\/div>
STMIB, STMDA,STMDB \uac00 \uc0ac\uc6a9\ub41c\ub2e4.<\/span><\/div>

<\/span><\/div>
\uc911\uc694\ud55c \uac83\uc740 \uc2a4\ud0dd\uacfc \uad00\ub828\ud574\uc11c \uc2e4\uc81c \uc0ac\uc6a9\ud560 \ub54c, \uc30d\uc73c\ub85c \uc0ac\uc6a9\ud55c\ub2e4\ub294 \uac83\uc774\ub2e4.<\/span><\/div>

<\/span><\/div>
LDMFD\/STMFD \uc815\ub3c4\ub9cc \uc798 \uc0ac\uc6a9\ud558\uba74 \ub41c\ub2e4. \uc790\uc138\ud55c \uc0ac\ud56d\uc740 ADS \ubb38\uc11c\ub97c \ucc38\uace0\ud558\uae30 \ubc14\ub780\ub2e4.<\/span><\/div>

<\/span><\/div>
\uc608)<\/span><\/div>

<\/span><\/div>
STMFD sp!, {r4-r6, lr} ; \uc2a4\ud0dd\uc5d0 r4-r6\uc640 lr \ub808\uc9c0\uc2a4\ud130\ub97c \uc800\uc7a5\ud558\uace0 sp\ub97c \uadf8\ub9cc\ud07c \uac10\uc18c\uc2dc\ud0a8\ub2e4.<\/span><\/div>

<\/span><\/div>
LDMFD sp!, {r4-r6, pc} ; \uc2a4\ud0dd\uc5d0\uc11c r4-r6\uc640 pc\ub97c \ubcf5\uc6d0\ud558\uace0 sp\ub97c \uadf8\ub9cc\ud07c \uc99d\uac00\uc2dc\ud0a8\ub2e4.<\/span><\/div>

<\/span><\/div>

<\/span><\/div>
ARM Developer Suite(ADS) 1.2 \uc5d0\uc11c C \ucf54\ub4dc\uc640 ASM \ucf54\ub4dc \uc11e\uc5b4 \uc4f0\uae30<\/span><\/div>

<\/span><\/div>
1. C \ucf54\ub4dc \ub0b4\uc5d0 \uc5b4\uc148\ube14\ub9ac \ucf54\ub4dc\ub97c inline\uc73c\ub85c \uc0ac\uc6a9\ud558\uae30<\/span><\/div>

<\/span><\/div>
(1) \uc0ac\uc6a9\ubc29\uc2dd<\/span><\/div>
asm(\"instruction[;instruction]\");<\/span><\/div>

<\/span><\/div>
\ub610\ub294 C \ucef4\ud30c\uc77c\ub7ec\uc758 \uad6c\ubb38\uc744 \uc0ac\uc6a9\ud558\uba74 \ub2e4\uc74c\uacfc \uac19\ub2e4.<\/span><\/div>

<\/span><\/div>
__asm<\/span><\/div>

<\/span><\/div>
{<\/span><\/div>

<\/span><\/div>
instruction [; instruction]<\/span><\/div>

<\/span><\/div>
...<\/span><\/div>

<\/span><\/div>
[instruction]<\/span><\/div><\/div><\/font><\/div><\/div>\n\n\n
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