{"id":714,"date":"2016-11-29T16:00:47","date_gmt":"2016-11-30T01:00:47","guid":{"rendered":"\/blog\/?p=714"},"modified":"2023-09-21T09:37:52","modified_gmt":"2023-09-21T00:37:52","slug":"avr-%ec%96%b4%ec%85%88%eb%b8%94%eb%a6%ac%ec%96%b4-%ec%a0%95%eb%a6%ac","status":"publish","type":"post","link":"https:\/\/hasu0707.duckdns.org\/blog\/?p=714","title":{"rendered":"AVR \uc5b4\uc148\ube14\ub9ac\uc5b4 \uc815\ub9ac"},"content":{"rendered":"\n

\ucd9c\ucc981 : http:\/\/blog.naver.com\/hsmc77?Redirect=Log&logNo=47507888<\/span><\/font><\/p>\r\n

\ucd9c\ucc982 : http:\/\/cafe.naver.com\/allcyber.cafe?iframe_url=\/ArticleRead.nhn%3Farticleid=1023<\/span><\/font><\/p>\r\n

\ucd9c\ucc983 : http:\/\/cafe.naver.com\/circuitsmanual\/184455<\/span><\/font><\/p>\r\n


<\/span><\/font><\/p>\r\n

\u25a0 \ub370\uc774\ud130 \uc2dc\ud2b8<\/span><\/font><\/p>\r\n

atmega328_datasheet.pdf<\/a>\r\n
<\/span><\/font><\/p>\r\n

atmega328_datasheet.pdf<\/a>\r\n
<\/span><\/font><\/p>\r\n


<\/p>\r\n


<\/p>\r\n

1. AVR \uc785\ucd9c\ub825\ud3ec\ud2b8 \ub808\uc9c0\uc2a4\ud130 \uc815\ub9ac<\/span><\/strong><\/span><\/font><\/p>\r\n


<\/span><\/font><\/p>\r\n

VR \ud3ec\ud2b8\uc758 \ub808\uc9c0\uc2a4\ud130\ub294 3\uc885\ub958\uac00 \uc788\uc2b5\ub2c8\ub2e4.<\/span><\/font><\/p>\r\n


<\/span><\/font><\/p>\r\n

\uc785\ub825 \ub808\uc9c0\uc2a4\ud130 PINx<\/span><\/font><\/p>\r\n

\ucd9c\ub825 \ub808\uc9c0\uc2a4\ud130 PORTx<\/span><\/font><\/p>\r\n

\uc785\ucd9c\ub825 \ubc29\ud5a5 \uc124\uc815 \ub808\uc9c0\uc2a4\ud130  DDRx<\/span><\/font><\/p>\r\n


<\/span><\/font><\/p>\r\n

\ub370\uc774\ud130\uc2dc\ud2b8\ub97c \ubd10\uc57c\uaca0\uc8e0?<\/span><\/font><\/p>\r\n


<\/span><\/font><\/p>\r\n

\"reg.png\"\r\n<\/span><\/span><\/font><\/p>\r\n

\ud3ec\ud2b8A \ub808\uc9c0\uc2a4\ud130\ub9cc \ubcf5\uc0ac \ud588\uc2b5\ub2c8\ub2e4.<\/span>
<\/p>\r\n


<\/span><\/font><\/p>\r\n

R\/W\ub77c\uace0 \uc801\ud78c \ubd80\ubd84\uc740 \uc77d\uae30\/\uc4f0\uae30\uac00 \ubaa8\ub450 \uac00\ub2a5\ud558\ub2e4\ub294 \ub73b\uc785\ub2c8\ub2e4.<\/span><\/font><\/p>\r\n

R\uc774\ub77c\uace0\ub9cc \uc801\ud78c \ube44\ud2b8\ub3c4 \uc788\ub294\ub370 Read\ub9cc \uac00\ub2a5\ud558\ub2e4\ub294 \ub73b\uc774\uace0<\/span><\/font><\/p>\r\n

(\uc774 \uadf8\ub9bc\uc5d0\ub294 \uc5c6\uc9c0\ub9cc) W\ub77c\uace0\ub9cc \uc801\ud78c \ube44\ud2b8\ub294 Write\ub9cc \uac00\ub2a5\ud558\ub2e4\ub294 \ub73b\uc785\ub2c8\ub2e4.<\/span><\/font><\/p>\r\n


<\/p>\r\n

\ub9ac\uc14b \ucd08\uae30 \uac12\uc740<\/span><\/font><\/p>\r\n

DDRx=0 \uc785\ub825<\/span><\/font><\/p>\r\n

PORTx=0 \ub0b4\ubd80 \ud480\uc5c5\uc800\ud56d \uc0ac\uc6a9 \uc548\ud568 \uc785\ub2c8\ub2e4.<\/span><\/font><\/p>\r\n

PINA\uc5d0 N\/A\ub85c \ub418\uc5b4 \uc788\ub294 \uc774\uc720\ub294<\/span><\/font><\/p>\r\n

\uacc4\uc18d\ud574\uc11c \ud540\uc5d0 \uac78\ub824\uc788\ub294 \uac12\uc73c\ub85c \uac31\uc2e0 \ub418\ubbc0\ub85c \ucd08\uae30\uac12\uc744 \uc904 \ud544\uc694\uac00 \uc5c6\uae30 \ub54c\ubb38\uc785\ub2c8\ub2e4.<\/span><\/font><\/p>\r\n

\uba85\uce6d\uc5d0\uc11c\ub3c4 \ub179\uc0c9\uc758 \uc0ac\uac01\ud615\uc744 \ubcf4\uba74 Register\ub77c\uace0 \uc801\ud600\uc788\uc9c0 \uc54a\uace0 Address\ub77c\uace0 \uc801\ud600\uc788\uc2b5\ub2c8\ub2e4.<\/span><\/font><\/p>\r\n


<\/p>\r\n

2. AVR \uba85\ub839\uc5b4 \uc815\ub9ac<\/span><\/o:p><\/font><\/span><\/strong><\/font><\/p>\r\n

<\/font> <\/span><\/p>\r\n

1. \uc804\uccb4 \uba85\ub839\uc5b4 \uc815\ub9ac<\/span><\/o:p><\/span><\/strong><\/font><\/p>\r\n

Rd: Destination (and source) register in the register file<\/span> <\/span>
<\/a>Rr: Source register in the register file<\/span> <\/span>
<\/a>b: Constant (0-7), can be a constant expression<\/span> <\/span>
<\/a>s: Constant (0-7), can be a constant expression<\/span> <\/span>
<\/a>P: Constant (0-31\/63), can be a constant expression<\/span> <\/span>
<\/a>K6; Constant (0-63), can be a constant expression<\/span> <\/span>
<\/a>K8: Constant (0-255), can be a constant expression<\/span> <\/span>
<\/a>k: Constant, value range depending on instruction. Can be a constant expression<\/span> <\/span>
<\/a>q: Constant (0-63), can be a constant expression<\/span> <\/span>
<\/a>Rdl:  R24, R26, R28, R30. For ADIW and SBIW instructions<\/span> <\/span>
<\/a>X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)<\/span><\/o:p><\/span><\/font><\/p>\r\n

<\/a>Arithmetic and Logic Instructions<\/span><\/o:p><\/span><\/font><\/h3>

Mnemonic<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Operands<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Description<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Operation<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Flags<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Cycles<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ADD <\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,Rr <\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Add without Carry <\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd + Rr <\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,H,S <\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ADC<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Add with Carry<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd + Rr + C<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,H,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SUB<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Subtract without Carry<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd - Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,H,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SUBI<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,K8<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Subtract Immediate<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd - K8<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,H,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SBC<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Subtract with Carry<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd - Rr - C<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,H,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SBCI<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,K8<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Subtract with Carry Immedtiate<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd - K8 - C<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,H,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

AND<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Logical AND<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd \u00b7 Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,N,V,S <\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ANDI<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,K8<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Logical AND with Immediate<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd \u00b7 K8<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

OR<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Logical OR<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd V Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ORI<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,K8<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Logical OR with Immediate<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd V K8<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

EOR<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Logical Exclusive OR<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd EOR Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

COM<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

One's Complement<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = $FF - Rd<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

NEG<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Two's Complement<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = $00 - Rd<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,H,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SBR<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,K8<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Set Bit(s) in Register<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd V K8<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CBR<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,K8<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Clear Bit(s) in Register<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd \u00b7 ($FF - K8)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

INC<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Increment Register<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

DEC<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Decrement Register<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd -1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

TST<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Test for Zero or Negative<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rd \u00b7 Rd<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CLR<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Clear Register<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = 0<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SER<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Set Register<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = $FF<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ADIW<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rdl,K6<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Add Immediate to Word<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rdh:Rdl = Rdh:Rdl + K6 <\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SBIW<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rdl,K6<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Subtract Immediate from Word<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rdh:Rdl = Rdh:Rdl - K 6<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

MUL<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Multiply Unsigned<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

R1:R0 = Rd * Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

MULS<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Multiply Signed<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

R1:R0 = Rd * Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

MULSU<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Multiply Signed with Unsigned<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

R1:R0 = Rd * Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

FMUL<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Fractional Multiply Unsigned<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

R1:R0 = (Rd * Rr) << 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

FMULS<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Fractional Multiply Signed<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

R1:R0 = (Rd *Rr) << 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

FMULSU<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd,Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Fractional Multiply Signed with Unsigned<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

R1:R0 = (Rd * Rr) << 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr><\/tbody><\/table>

 <\/span> <\/span><\/o:p><\/span><\/font><\/p>\r\n

<\/a>Branch Instructions<\/span><\/o:p><\/span><\/font><\/h3>

Mnemonic<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Operands<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Description<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Operation<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Flags<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Cycles<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

RJMP<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Relative Jump<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

PC = PC + k +1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

IJMP<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Indirect Jump to<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

PC = Z<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

EIJMP<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Extended Indirect Jump (<\/span>Z<\/span><\/font><\/span><\/tt><\/a>)<\/span><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

STACK = PC+1, PC(15:0) = Z, PC(21:16) = EIND<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

JMP<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Jump <\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

PC = k<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

RCALL<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Relative Call Subroutine<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

STACK = PC+1, PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

3\/4*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ICALL<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Indirect Call to (<\/span>Z<\/span><\/font><\/span><\/tt><\/a>)<\/span><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

STACK = PC+1, PC = Z <\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

3\/4*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

EICALL<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Extended Indirect Call to (<\/span>Z<\/span><\/font><\/span><\/tt><\/a>)<\/span><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

STACK = PC+1, PC(15:0) = Z, PC(21:16) =EIND<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

4*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CALL<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Call Subroutine<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

STACK = PC+2, PC = k<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

4\/5*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

RET<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Subroutine Return<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

PC = STACK<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

4\/5*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

RETI<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Interrupt Return<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

PC = STACK<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

I<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

4\/5*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CPSE<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Compare, Skip if equal <\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if (Rd ==Rr) PC = PC 2 or 3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2\/3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CP<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Compare<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd -Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,H,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CPC<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Compare with Carry<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd - Rr - C<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,H,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CPI<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>K8<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Compare with Immediate<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd - K<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,H,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SBRC<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rr<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>b<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Skip if bit in register cleared<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(Rr(b)==0) PC = PC + 2 or 3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2\/3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SBRS<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rr<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>b<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Skip if bit in register set<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(Rr(b)==1) PC = PC + 2 or 3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2\/3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SBIC<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

P<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>b<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Skip if bit in I\/O register cleared<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(I\/O(P,b)==0) PC = PC + 2 or 3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2\/3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SBIS<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

P<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>b<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Skip if bit in I\/O register set<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(I\/O(P,b)==1) PC = PC + 2 or 3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2\/3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRBC<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

s<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if Status flag cleared<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(SREG(s)==0) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRBS<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

s<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if Status flag set<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(SREG(s)==1) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BREQ<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if equal<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(Z==1) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRNE<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if not equal<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(Z==0) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRCS<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if carry set<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(C==1) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRCC<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if carry cleared<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(C==0) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRSH<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if same or higher<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(C==0) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRLO<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if lower<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(C==1) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRMI<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if minus<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(N==1) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRPL<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if plus<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(N==0) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRGE<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if greater than or equal (signed)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(S==0) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRLT<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if less than (signed)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(S==1) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRHS<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if half carry flag set<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(H==1) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRHC<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if half carry flag cleared<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(H==0) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRTS<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if T flag set<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(T==1) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRTC<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if T flag cleared<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(T==0) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRVS<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if overflow flag set<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(V==1) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRVC<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if overflow flag cleared<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(V==0) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRIE<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if interrupt enabled<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(I==1) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BRID<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Branch if interrupt disabled<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

if(I==0) PC = PC + k + 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1\/2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr><\/tbody><\/table>

<\/a> <\/span><\/o:p><\/span><\/font><\/h3>

Data Transfer Instructions<\/span><\/o:p><\/font><\/span><\/font><\/h3>

Mnemonic<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Operands<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Description<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Operation<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Flags<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Cycles<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

MOV<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Copy register<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

MOVW<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Copy register pair<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd+1:Rd = Rr+1:Rr, r,d even<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LDI<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>K8<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Immediate<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = K<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LDS<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>k<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Direct<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = (k)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LD<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>X<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Indirect<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = (X)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LD<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>X+<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Indirect and Post-Increment<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = (X), X=X+1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LD<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>-X<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Indirect and Pre-Decrement<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

X=X-1, Rd = (X)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LD<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Y<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Indirect<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = (Y)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LD<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Y+<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Indirect and Post-Increment<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = (Y), Y=Y+1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LD<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>-Y<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Indirect and Pre-Decrement<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Y=Y-1, Rd = (Y)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LDD<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span>Y<\/span><\/font><\/span><\/tt><\/a>+<\/span><\/font>q<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Indirect with displacement<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = (Y+q)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LD<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Z<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Indirect <\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = (Z)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LD<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Z+<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Indirect and Post-Increment<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = (Z), Z=Z+1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LD<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>-Z<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Indirect and Pre-Decrement<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z=Z-1, Rd = (Z)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LDD<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span>Z<\/span><\/font><\/span><\/tt><\/a>+<\/span><\/font>q<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Indirect with displacement<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = (Z+q)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

STS<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

k,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Store Direct<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

(k) = Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ST<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

X<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Store Indirect<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

(X) = Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ST<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

X+<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Store Indirect and Post-Increment<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

(X) = Rr, X=X+1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ST<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

-X<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Store Indirect and Pre-Decrement<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

X=X-1, (X)=Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ST<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Y<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Store Indirect<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

(Y) = Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2*<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ST<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Y+<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Store Indirect and Post-Increment<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

(Y) = Rr, Y=Y+1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ST<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

-Y<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Store Indirect and Pre-Decrement<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Y=Y-1, (Y) = Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ST<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Y<\/span><\/font><\/span><\/tt><\/a>+<\/span>q<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Store Indirect with displacement<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

(Y+q) = Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ST<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Store Indirect<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

(Z) = Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ST<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z+<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Store Indirect and Post-Increment<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

(Z) = Rr, Z=Z+1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ST<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

-Z<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Store Indirect and Pre-Decrement<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z=Z-1, (Z) = Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ST<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z<\/span><\/font><\/span><\/tt><\/a>+<\/span>q<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Store Indirect with displacement<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

(Z+q) = Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LPM<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Program Memory<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

R0 = (<\/span>Z<\/span><\/font><\/span><\/tt><\/a>)<\/span><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LPM<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Z<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Program Memory<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = (<\/span>Z<\/span><\/font><\/span><\/tt><\/a>)<\/span><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LPM<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Z+<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Load Program Memory and Post-Increment<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = (<\/span>Z<\/span><\/font><\/span><\/tt><\/a>), Z=Z+1<\/span><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ELPM<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Extended Load Program Memory<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

R0 = (RAMPZ:<\/span>Z<\/span><\/font><\/span><\/tt><\/a>)<\/span><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ELPM<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Z<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Extended Load Program Memory<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = (RAMPZ:<\/span>Z<\/span><\/font><\/span><\/tt><\/a>)<\/span><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ELPM<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Z+<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Extended Load Program Memory and Post Increment<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = (RAMPZ:<\/span>Z<\/span><\/font><\/span><\/tt><\/a>), Z = Z+1<\/span><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

3<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SPM<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Store Program Memory<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

(<\/span>Z<\/span><\/font><\/span><\/tt><\/a>) = R1:R0<\/span><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

-<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ESPM<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Extended Store Program Memory<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

(RAMPZ:<\/span>Z<\/span><\/font><\/span><\/tt><\/a>) = R1:R0<\/span><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

-<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

IN<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>P<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

In Port<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = P<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

OUT<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

P<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Out Port<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

P = Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

PUSH<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rr<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Push register on Stack<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

STACK = Rr<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

POP<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Pop register from Stack<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd = STACK<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr><\/tbody><\/table>

* Cycle times for data memory accesses assume internal memory accesses and are not valid for accesses through the external RAM interface. For the LD, ST, LDD, STD, LDS, STS, PUSH and  POP instructions, add one cycle plus one cycle for each wait state.<\/span> <\/span><\/o:p><\/span><\/font><\/p>\r\n

<\/a>Bit and Bit-test Instructions<\/span><\/o:p><\/span><\/font><\/h3>

Mnemonic<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Operands<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Description<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Operation<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Flags<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Cycles<\/span><\/strong><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LSL<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Logical shift left<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,H,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

LSR<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Logical shift right<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ROL<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rotate left through carry<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,H,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ROR<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rotate right through carry<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

ASR<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Arithmetic shift right<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd(n)=Rd(n+1), n=0,...,6<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z,C,N,V,S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SWAP<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Swap nibbles<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BSET <\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

s<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Set flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

SREG(s) = 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

SREG(s)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BCLR<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

s<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Clear flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

SREG(s) = 0<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

SREG(s)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SBI<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

P<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>b<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Set bit in I\/O register<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

I\/O(P,b) = 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CBI<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

P<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>b<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Clear bit in I\/O register<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

I\/O(P,b) = 0<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

2<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BST<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rr<\/span><\/font><\/span><\/tt><\/a>,<\/span><\/font>b<\/span><\/font><\/span><\/tt><\/a><\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Bit store from register to T<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

T = Rr(b)<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

T<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

BLD<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd<\/span><\/font><\/span><\/tt>,<\/span>b<\/span><\/tt><\/o:p><\/span><\/font><\/font><\/p>\r\n<\/td>

Bit load from register to T<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Rd(b) = T<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SEC<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Set carry flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

C =1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

C<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CLC<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Clear carry flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

C = 0<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

C<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SEN<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Set negative flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

N = 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

N<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CLN<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Clear negative flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

N = 0<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

N<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SEZ<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Set zero flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z = 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CLZ<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Clear zero flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z = 0<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Z<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SEI<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Set interrupt flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

I = 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

I<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CLI<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Clear interrupt flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

I = 0<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

I<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SES<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Set signed flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

S = 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CLN<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Clear signed flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

S = 0<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

S<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SEV<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Set overflow flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

V = 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

V<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CLV<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Clear overflow flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

V = 0<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

V<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SET<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Set T-flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

T = 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

T<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CLT<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Clear T-flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

T = 0<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

T<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SEH<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Set half carry flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

H = 1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

H<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

CLH<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Clear half carry flag<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

H = 0<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

H<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

NOP<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

No operation<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

SLEEP<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Sleep<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

See instruction manual<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr>

WDR<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

Watchdog Reset<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

See instruction manual<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

None<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td>

1<\/span><\/o:p><\/font><\/span><\/font><\/p>\r\n<\/td><\/tr><\/tbody><\/table>



<\/o:p><\/span><\/font><\/p>\r\n

2. AVR ASM \uc5d0\uc11c \uc0ac\uc6a9\ud558\ub294 \uc608\uc57d\uc5b4.<\/span><\/o:p><\/span><\/strong><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

1) BYTE<\/span> <\/span><\/span>\u2013<\/span><\/font><\/span> <\/span>byte \ubcc0\uc218 \uc9c0\uc815<\/span>
           <\/span> <\/span><\/span>.DSEG<\/span><\/span> <\/span>
           <\/span> <\/span><\/span>var1:    .BYTE 1            ; reserve 1 byte to var1<\/span><\/span> 

<\/a><\/span><\/font><\/p>\r\n

2) CSEG - Code segment \uc9c0\uc815<\/a><\/span><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

3) DB - Define constant byte(s) in program memory and EEPROM<\/span><\/font><\/p>\r\n

           <\/span> <\/span><\/font>.CSEG<\/span><\/font><\/span><\/span> <\/span>
           <\/span> <\/span><\/span><\/span><\/span>consts: .DB 0, 255, 0b01010101, -128, 0xaa<\/span><\/span><\/font><\/span><\/p>\r\n

           <\/span> <\/span><\/span>.ESEG<\/span><\/span> <\/span>
           <\/span> <\/span><\/span>const2: .DB 1,2,3<\/span><\/span><\/a><\/span><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

4) DEF - Set a symbolic name on a register<\/span><\/font><\/p>\r\n

           <\/span> <\/span><\/font>.DEF temp=R16<\/span><\/font><\/span><\/span>
           <\/span> <\/span>.DEF ior=R0<\/span><\/o:p><\/span><\/span><\/span><\/font><\/p>\r\n

<\/a> <\/span><\/o:p><\/span><\/strong><\/font><\/p>\r\n

5)<\/span><\/strong> <\/span>DEVICE - Define which device to assemble for<\/span><\/span><\/font><\/p>\r\n

           <\/span> <\/span><\/font>Syntax:<\/span> <\/span>
<\/font>           <\/span> <\/span><\/font><\/span>.DEVICE AT90S1200 |AT90S2313 | AT90S2323 | AT90S2333 | AT90S2343 | AT90S4414<\/span><\/o:p><\/span><\/span><\/font><\/p>\r\n

           <\/span> <\/span><\/font>| AT90S4433 | AT90S4434 | AT90S8515 | AT90S8534 | AT90S8535 | ATtiny11 | ATtiny12<\/span><\/o:p><\/font><\/span><\/span><\/font><\/p>\r\n

           <\/span> <\/span><\/font>| ATtiny22 | ATmega603 | ATmega103<\/span><\/o:p><\/font><\/span><\/span><\/font><\/p>\r\n

           <\/span> <\/span><\/font>Example:<\/span><\/font><\/span><\/font><\/p>\r\n

           <\/span> <\/span><\/font>.DEVICE AT90S1200  ; Use the AT90S1200<\/span><\/a><\/o:p><\/font><\/span><\/span><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

6) DSEG - Data Segment<\/span><\/font><\/p>\r\n

           <\/span> <\/span><\/span>.DSEG                        ; Start data segment<\/span><\/span><\/font><\/span><\/p>\r\n

           <\/span> <\/span><\/font>var1:  .BYTE 1               ; reserve 1 byte to var1<\/span><\/font><\/span><\/span> <\/span>
           <\/span> <\/span><\/span>table:  .BYTE tab_size       ; reserve tab_size bytes.<\/span><\/span><\/a><\/span><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

7) DW - Define constant word(s) in program memory and EEPROM<\/span><\/font><\/p>\r\n

           <\/span> <\/span><\/span>.CSEG<\/span><\/span> <\/span>
           <\/span> <\/span><\/span>varlist:  .DW 0, 0xffff, 0b1001110001010101, -32768, 65535<\/span><\/span><\/font><\/span><\/p>\r\n

           <\/span> <\/span><\/span>.ESEG<\/span><\/span> <\/span>
           <\/span> <\/span><\/span>eevarlst: .DW 0,0xffff,10<\/span><\/span><\/a><\/span><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

8<\/span><\/strong>) ENDMACRO - End macro<\/span><\/font><\/p>\r\n

           <\/span> <\/span><\/span>.MACRO SUBI16               ; Start macro definition<\/span><\/span> <\/span>
<\/span>       <\/span> <\/span>                       <\/span> <\/span>subi r16,low(@0)    ; Subtract low byte<\/span><\/span><\/span> <\/span>
<\/span>       <\/span> <\/span>                       <\/span> <\/span>sbci r17,high(@0)   ; Subtract high byte<\/span><\/span><\/span> <\/span>
           <\/span> <\/span><\/span>.ENDMACRO<\/span><\/span><\/a><\/span><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

9<\/span><\/strong>) EQU - Set a symbol equal to an expression<\/span><\/font><\/p>\r\n

           <\/span> <\/span><\/span>.EQU io_offset = 0x23<\/span><\/span> <\/span>
           <\/span> <\/span><\/span>.EQU porta     = io_offset + 2<\/span><\/span><\/a><\/span><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

10<\/span><\/strong>) ESEG - EEPROM Segment<\/span><\/font><\/p>\r\n

           <\/span> <\/span><\/span>.ESEG<\/span><\/span> <\/span>
           <\/span> <\/span><\/span>eevar1: .DW 0xffff        ; initialize 1 word in EEPRO<\/span><\/span>M <\/span><\/a><\/span><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

11<\/span><\/strong>) EXIT - Exit this file. \uc774 \uc608\uc57d\uc5b4 \uc774\ud6c4\uc758 \ucf54\ub4dc\ub294 \uc5b4\uc148\ube14\ud558\uc9c0\uc54a\ub294\ub2e4.<\/span><\/a><\/span><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

12) INCLUDE - Include another file<\/a><\/span><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

13) LIST - Turn the listfile generation on<\/span><\/font><\/p>\r\n

           <\/span> <\/span><\/span>.NOLIST                ; Disable listfile generation<\/span><\/span> <\/span>
           <\/span> <\/span><\/span>.INCLUDE \"macro.inc\"   ; The included files will not<\/span><\/span> <\/span>
           <\/span> <\/span><\/span>.INCLUDE \"const.def\"   ; be shown in the listfile<\/span><\/span> <\/span>
           <\/span> <\/span><\/span>.LIST                  ; Reenable listfile generation<\/span><\/span><\/a><\/span><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

14) LISTMAC - Turn macro expansion on<\/a><\/span><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

15) MACRO - Begin macro<\/a><\/span><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

16) NOLIST - Turn listfile generation off<\/a><\/span><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

17<\/span><\/strong>) ORG - Set program origin<\/span><\/a><\/span><\/font><\/p>\r\n

 <\/span><\/o:p><\/span><\/font><\/p>\r\n

1<\/span>8<\/span><\/strong>) SET - Set a symbol equal to an expression<\/span><\/span><\/font><\/p>\r\n

           <\/span> <\/span><\/span>.SET io_offset = 0x23<\/span><\/span> <\/span>
           <\/span> <\/span><\/span>.SET porta     = io_offset + 2<\/span><\/span><\/font><\/span><\/p>\r\n

           <\/span> <\/span><\/span>.CSEG                 ; Start code segment<\/span><\/span> <\/span>
<\/span>       <\/span> <\/span>                       <\/span> <\/span>clr r2        ; Clear register 2<\/span><\/span><\/span> <\/span>
<\/span>       <\/span> <\/span>                       <\/span> <\/span>out porta,r2  ; Write to Port A<\/span><\/span><\/span><\/font><\/p>\r\n<\/div><\/td><\/tr><\/tbody><\/table>\n\n\n

atmega328_datasheet.pdf<\/a>\ub2e4\uc6b4\ub85c\ub4dc<\/a><\/div>\n\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_import_markdown_pro_load_document_selector":0,"_import_markdown_pro_submit_text_textarea":"","site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"footnotes":""},"categories":[13],"tags":[],"class_list":["post-714","post","type-post","status-publish","format-standard","hentry","category-computing_singleboardcomputer"],"_links":{"self":[{"href":"https:\/\/hasu0707.duckdns.org\/blog\/index.php?rest_route=\/wp\/v2\/posts\/714","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hasu0707.duckdns.org\/blog\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hasu0707.duckdns.org\/blog\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hasu0707.duckdns.org\/blog\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/hasu0707.duckdns.org\/blog\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=714"}],"version-history":[{"count":0,"href":"https:\/\/hasu0707.duckdns.org\/blog\/index.php?rest_route=\/wp\/v2\/posts\/714\/revisions"}],"wp:attachment":[{"href":"https:\/\/hasu0707.duckdns.org\/blog\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=714"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hasu0707.duckdns.org\/blog\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=714"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hasu0707.duckdns.org\/blog\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=714"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}